Stored charge non-volatile memory devices such as floating gate flash memory devices, for example, use charge on a floating gate of an MOS transistor to program the logic state of the transistor. FIG. 1 illustrates, in a somewhat idealized form not drawn to scale, the cross-section of a floating gate transistor, using an NMOS structure as an example (an equivalent PMOS device can also be made). The floating gate transistor includes a P-type silicon substrate with n+ source and drain diffusions which define the length of a channel region. Immediately above the channel is an insulating layer of oxide, typically silicon dioxide. Immediately above this oxide layer is the conductive floating gate, typically made of polysilicon. Immediately above the floating gate is another later of oxide, and above that layer is the control gate, typically another polysilicon gate. A passivating oxide layer, typically silicon dioxide, protects the above-described layers from contaminants.
Programming voltages can be applied to the transistor between the control gate and the substrate or source and drain diffusions to add or remove charge from the floating gate by hot carrier injection (HCI) or by Fowler-Nordheim tunneling (“programming” is used generically, herein, to refer to both program and erase operations). One figure of merit for a floating gate transistor is its programming efficiency. Programming efficiency is the time required to transition between the programmed and erased states for a giving programming voltage.
After the programming voltage is removed, the charge is retained on the floating gate because the floating gate is electrically isolated by the insulating oxide that prevents the charge from leaking to the channel, the source, the drain or the control gate of the transistor. The presence of charge on the floating gate causes a shift in the threshold voltage of the transistor, which is the gate-to-source voltage that turns the transistor on and allows current to flow from drain to source under an applied drain-to-source voltage.
For the NMOS device illustrated in FIG. 1, a positive voltage from the control gate to the substrate causes electrons to migrate from the channel to the floating gate, which raises the threshold voltage of the device (conventionally known as the “programmed” state). A negative voltage from the control gate to the substrate causes holes to migrate from the channel to the floating gate, which lowers the threshold voltage of the device (conventionally known as the “erased” state). The two different threshold voltages can be associated with different logic or data states (e.g., “1” and “0”). The voltage difference between the two thresholds, known as the sense window, is a measure of the integrity of the stored data.
A floating gate memory transistor can be read by applying a known gate-to-source voltage with a value between the programmed threshold voltage and the erased threshold voltage and sensing the current that flows through the memory transistor under an applied drain-to-source voltage. However, the read current can disturb the stored charge and cause leakage that reduces the sense window. If a large number of reads are performed without an intervening program or erase operation, the integrity of the stored data may be lost. In a floating gate device, such as that illustrated in FIG. 1, the floating gate is not directly accessible for measurement, so the only way to sense the state of the device is to sense the read current.
One approach to this problem has been to synthesize a floating gate memory device from two conventional, series-connected MOS transistors and to directly sense the voltage on the floating gate, where the voltage on the floating gate in the programmed and erased states is approximately equal to the threshold voltage shift associated with a conventional floating gate memory transistor. If the voltage is sensed with a high input impedance sense amplifier, then the stored charge is not disturbed. In this approach, one MOS transistor is configured as a capacitor (MOS capacitor) and the other transistor is configured as a tunnel diode (MOS tunnel diode). The programming efficiency of this configuration depends on a coupling coefficient between the MOS capacitor and the MOS tunnel diode. For efficient programming, the ratio of the capacitance of the MOS capacitor to the capacitance of the MOS tunnel diode should be a large as possible. However, conventional CMOS (complementary MOS) fabrication processes, using self-aligning gates, limits the capacitance per unit area of the MOS capacitor, requiring large areas of silicon to achieve the required capacitance.